Debugging#
On-chip debug. A probe on one end, a gdb-server in the middle, gdb on the other end, and the chip stopped under inspection. The operator gains full visibility (registers, memory, peripherals, stack traces) without printf statements that change the timing of the bug. The stack is JTAG or SWD on the wire, OpenOCD or J-Link as the daemon, and gdb (or a gdb front-end) as the user interface.
The stack#
Layer |
Component |
|---|---|
Wire protocol |
|
Probe |
ST-Link, J-Link, BlackMagic Probe, CMSIS-DAP, J-Link Edu; see Programmers. |
Server |
OpenOCD, |
Client |
|
Side channels#
Print-style debug output without the cost of an extra UART pin.
Mechanism |
Note |
|---|---|
Semihosting |
|
ITM / SWO |
Cortex-M only. A small FIFO on-chip; the CPU writes a byte, SWO trace pin clocks it out to the probe at line rate. Non-intrusive. |
RTT (SEGGER) |
Ring buffers in RAM polled by the probe; the fastest
trace channel available, no extra pin needed beyond
SWD. |
Live watch (Cortex-M) |
Probe reads target RAM while the CPU runs; configuration in the IDE. |
gdb basics#
Command |
Effect |
|---|---|
|
Attach to an OpenOCD gdb server on the default port. |
|
Reset the target and halt at the reset vector. |
|
Program the ELF into flash via the probe. |
|
Break at the named symbol. |
|
Resume execution. |
|
Single-step at the instruction level. |
|
Dump CPU registers. |
|
Show RTOS threads (with proper OpenOCD config). |
|
Examine 16 words of memory at the address. |
|
Walk the call stack. |
|
Stop when the location’s value changes. |
|
Patch a register; useful for recovering from a fault. |
References#
ARM Cortex-M3 / M4 Devices Generic User Guide for the fault-handling register layout.
Programmers for the probe selection.